The present invention relates to a semiconductor protection circuit of a semiconductor device, and more particularly, it relates to a circuit for protecting a device from charge entering an interconnect such as a word line provided in a nonvolatile semiconductor memory, and a method for operating the same.
In accordance with recently increased degree of integration and reduced cost of a nonvolatile semiconductor memory, a MONOS (metal-oxide-nitride-oxide-silicon) memory technique in which a virtual ground type array is used and charge is locally trapped in an insulating film disposed beneath a gate electrode has been proposed.
In a MONOS memory, when a high (positive or negative) voltage is applied to a word line owing to charge generated during the fabrication, the threshold voltage of a memory cell is varied, and therefore, it is necessary to provide a circuit for protecting a word line or a charge trapping layer from the charge generated during the fabrication.
Now, a conventional semiconductor protection circuit will be described with reference to drawings.
First, a first conventional technique will be described (see U.S. Pat. Nos. 6,337,502 and 6,117,714). A conventional MONOS memory includes a plurality of memory cells arranged in the form of a matrix; word lines provided correspondingly to the rows of the memory cells and respectively connected to gate electrodes of MONOS structures included in the corresponding memory cells; bit lines provided correspondingly to the columns of the memory cells and respectively connected to impurity diffusion layers of the corresponding memory cells; an X decoder for driving the word lines; a Y decoder connected to the bit lines; and a sense amplifier for amplifying a signal read by the Y decoder. Each memory cell includes a P-type well formed in a P-type substrate; a charge trapping layer and a word line electrode successively formed on the P-type well in this order in the upward direction; N-type diffusion layers formed in the P-type well on both sides of the charge trapping layer; a word line formed above the word line electrode and made of a first layer metal interconnect; and a contact for connecting the word line electrode and the first layer metal interconnect. The bit line is connected to the N-type diffusion layer (i.e., the source or drain) of the memory cell.
FIG. 13 is a circuit diagram of a conventional semiconductor protection circuit. It is noted that this drawing shows a state attained during the fabrication, and specifically, it shows a state of the conventional semiconductor protection circuit attained after forming a first layer metal interconnect 1012. As shown in FIG. 13, the first layer metal interconnect 1012 for connecting a word line of a memory cell and an X decoder is connected to the drain of an N-channel MOS transistor 1102 (hereinafter referred to as the NMOS 1102) disposed in a P-type well PW. The drain of the NMOS 1102 also functions as an N-type diffusion layer included in a backward diode 1103. The source of the NMOS 1102 is grounded and the gate electrode thereof is connected to an antenna formed by using the first layer metal interconnect 1012 or the like.
FIG. 14 is a cross-sectional view of the conventional semiconductor protection circuit of FIG. 13. It is noted that this drawing shows a state thereof attained during the fabrication, and for example, it shows a state of the conventional semiconductor protection circuit attained during formation of a first layer metal interconnect 1012. As shown in FIG. 14, the conventional semiconductor protection circuit includes a P-type well 1003 provided in a P-type semiconductor substrate 1001; an isolation insulating film 1005 formed on the P-type well 1003; a gate insulating film 1008 and a gate electrode 1009b provided on the P-type well 1003; N-type diffusion layers 1007 including an N-type impurity and provided in the P-type well 1003 on both sides of the gate electrode 1009b; and a P-type diffusion layer 1006 formed on the P-type well 1003 to be in contact with one N-type diffusion layer 1007. A word line electrode 1009a of a memory cell is connected to the first layer metal interconnect 1012 through a contact 1011a and is connected to one N-type diffusion layer 1007 working as the drain of the NMOS 1102 through a contact 1011b. Since the other N-type diffusion layer 1007 working as the source of the NMOS 1102 is connected to the P-type diffusion layer 1006, it has the same potential as the P-type well 1003, namely, the ground potential.
FIG. 15 is a diagram for showing a method for protecting a memory cell from positive charge by the conventional semiconductor protection circuit. When positive charge enters the first layer metal interconnect 1012, the drain voltage of the NMOS 1102 is increased in the positive direction. Simultaneously, since the potential of the antenna 1104 connected to the gate of the NMOS 1102 is also increased in the positive direction, the NMOS 1102 is turned on, and hence, the drain and the source of the NMOS 1102 are connected to each other. Accordingly, the positive charge transferred to the drain of the NMOS 1102 can be drained to the ground. Specifically, when the threshold voltage of the NMOS 1102 is approximately 1 V, the potential increase of the word line electrode 1009a caused by positive charge can be suppressed to approximately 1 V.
FIG. 16 is a diagram for showing a method for protecting a memory cell from negative charge by the conventional semiconductor protection circuit. When negative charge enters the first layer metal interconnect 1012, the negative charge can be drained to the ground through the backward diode 1103.
FIG. 17 is a circuit diagram of the conventional semiconductor protection circuit obtained after completing the fabrication. The conventional semiconductor protection circuit is characterized by the gate electrode and the source of the NMOS 1102 being grounded.
FIG. 18 is a cross-sectional view of the conventional semiconductor protection circuit of FIG. 17 obtained after completing the fabrication. The word line electrode 1009a is connected to the first layer metal interconnect 1012 through the contact 1011a and is further connected to a second layer metal interconnect 1014 through a first via 1013a to be connected to the X decoder through the second layer metal interconnect 1014a. The gate electrode 1009b of the NMOS 1102 is connected to the first layer metal interconnect 1012 through a contact 1011c, is further connected to a second layer metal interconnect 1014b through a first via 1013b and is further connected to a third layer metal interconnect 1016 through a second via 1015, so as to be grounded through the vias and the contact.
In this manner, as a characteristic of this conventional technique, while the metal interconnect connected to a word line is being processed, the gate electrode 1009b is placed in a floating state connected to the antenna, and after completing the processing of the metal interconnect connected to a word line, the potential of the gate electrode 1009b is suppressed to the ground potential.
In a data write operation, a voltage of, for example, approximately +9 V is applied to a word line of the semiconductor memory. At this point, the NMOS 1102 is in an off state because its gate electrode is grounded, and hence, the voltage of 9 V applied to the word line is never dropped. Also, since a reverse voltage is applied to the backward diode 1103, no current passes, and hence, the applied voltage is never dropped by the conduction of the backward diode. Accordingly, the voltage of approximately +9 V can be applied to the word line of the memory cell 1101.
In a data delete operation, a voltage of approximately 0 V (substantially equal to the ground potential) is applied to the word line of the memory cell 1101. At this point, the NMOS 1102 is in an off state because its gate electrode is grounded, and hence, the voltage of 0 V applied to the word line is never changed. Also, since the same potential is applied to both ends of the backward diode 1103, the voltage applied to the word line is never changed by the conduction of the backward diode 1103. Accordingly, the voltage of approximately +0 V can be applied to the word line.